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Power consumption - crudely measured as battery life - is a critical design goal for any portable system. The OMAP35x devices include power management techniques that enable them to deliver high performance while consuming much less power traditionally associated at these performance levels. Unless these techniques are complimented with an equally power-efficient software; the benefits won't be visible. In this article, we begin with a brief look at hardware features related to the power management available in the OMAP35x devices.
This is followed by a quick introduction to the power management frameworks available in the Linux kernels; and how they have been adapted for the OMAP35x devices. To leverage the power savings built into the kernel, applications need to be equally disciplined to ensure that savings are actually realized. Generic guidelines that would help applications in achieving the desired savings are also discussed here. Since the Linux PSP package v1.
The contents will be updated shortly to bring out specific differences and provide information relevant to the community Linux. Once the system is powered-on, power is consumed while the device is busy with useful data processing as well as non-useful idle loops.
The OMAP35x devices include specific features to optimize the power consumption in both these scenarios. A Clock Domain refers to groups of modules that are fed same 'gated' clock signal. If all modules in the clock are inactive, the clock signal can be cut to lower the power consumption. The HW supervision eliminates software overheads and further increase power savings by much fine grain control of the clocks - not possible in software only implementation - specifically during active processing.
OMAP35x device provides mechanism for gating the clocks are various levels - from device, various levels in the clock tree upto the full clock domain. At device level, there are two types of clocks - functional and interface. The functional clock is required for internal working of the device. The interface clock is required for interfacing with the OCP bus. This allows the OCP bus to be turned off leaving the device functional.
A Power Domain refers to a section of device that is controlled a single power switch. These sections have independent power rails.
A voltage domain can contain one or more power domains. All modules in a voltage domain gets same voltage. Dedicated SmartReflex hardware implements a feedback loop - without processor intervention - which optimizes the voltage levels to account for differences in the manufacturing process, temperature and silicon degradation.
As name suggests, the cpuidle is excecuted when the Linux kernel enters the idle processing. This framework allows the system to transition between the different idle states C-states. Each idle state is characterized by:. If the system can perform necessary tasks at lower voltage, the power savings are quite evident from this equation:.
The DVFS has been implemented using the cpufreq framework. This framework allows system to transition between discrete frequencies P-states depending upon the active load. While the overall intent on a power efficient system is to aggressively conserve power, it cannot be done at cost of the end-user experience. A running system comprises multiple threads of execution - each with its own requirements on performance and acceptable latency.
An arbitration mechanism is required to ensure that system is performing in a 'state' that is acceptable to all running processes. The Constraint Framework is a mechanism for the device drivers and applications to specify their requirements in terms of acceptable interrupt latency and frequency. In a real-life system the applications cannot be started synchronously. If many applications use their own timers to perform specific actions, the probability of CPU to enter a deeper idle state is reduced.
Also, frequent entry and exit from an idle state will result in increased power consumption. Grouping the timers across the system help in reducing the wake-ups from an idle state. Indirectly, this will allow the system to enter deeper idle states and maintain the state for long. Contents 1 Introduction 2 Hardware feature for Power Management 2.